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Emulation Engineer - Graduate Intern
Location:
Hillsboro, OR
Description:
Job Description Role and Responsibilities: As a Emulation Engineer - Graduate Intern you will: Perform functional logic verification of an integrated SoC to ensure design will meet specifications. Execute verification plans on emulation platforms and verify the design, analyze power and performance, and uncover bugs. You will learn expert skillsets to replicate, root causes, and debugs issues that are spanning across critical flows. The work also gives immense learning to enhance project management skills by working with Sr engineers, SoC architects, and leads in both simulation/emulation and post-silicon environments to help introduce process flow improvements for efficient bug triaging and disposition. Your will gain immense knowledge of architecture and industry standard protocols that can aid in future career growth for Pcie/Memory/Coherency/Power/Security and more. You will be responsible for maintaining the quality of the deliverables and introducing any new flows that can improve validation turnaround time via bucketizing issues and indicator management to propose innovative ways to improve the process. Responsibilities may be quite diverse of a technical nature. U.S. experience and education requirements will vary significantly depending on the unique needs of the job. Job assignments are usually for the summer or for short periods during breaks from school. Qualifications You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences. Minimum Qualifications: Pursuing Master's degree in Electrical or Computer Engineering, Computer Science or in a related field of study Knowledge of logic design verification with various tools and methodologies like System Verilog, Perl, OVM/UVM etc. Preferred Qualifications: Experience with Pre-Silicon simulation tool flows such as Synopsys VCS Verdi and DVE or other is a plus Knowledge of some of the flows amongst PCIe, Power Management, Memory and Coherency is a plus Previous experience with bug triaging and/or indicator management is a plus Requirements listed could be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Inside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner. Other Locations US, Santa Clara Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. Annual Salary Range for jobs which could be performed in US, California: $63,000.00-$166,000.00*Salary range dependent on a number of factors including location and experience Working Model This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs. Requisition #: JR0258178pca3lyuhf
Company:
Intel
Posted:
May 10 on ITJobsWeb
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More About this Listing: Emulation Engineer - Graduate Intern
Emulation Engineer - Graduate Intern is a Engineering Engineer Job at Intel located in Hillsboro OR. Find other listings like Emulation Engineer - Graduate Intern by searching Oodle for Engineering Engineer Jobs.
Emulation Engineer - Graduate Intern is a Engineering Engineer Job at Intel located in Hillsboro OR. Find other listings like Emulation Engineer - Graduate Intern by searching Oodle for Engineering Engineer Jobs.